In integrated circuit (IC) manufacturing, a semiconductor wafer typically contains a plurality of testlines in the scribe line area between adjacent wafer dies. Each testline includes a number of devices under test (DUTs), which are structures similar to those that are normally used to form the integrated circuit products in the wafer die area. DUTs are usually formed in the test pattern areas between adjacent probe pads on a testline at the same time as the functional circuitry using the same process steps. Probe pads are usually flat, square metal surfaces on a testline through which test stimuli can be applied to corresponding DUTs. Parametric test results on DUTs are usually utilized to monitor, improve and refine a semiconductor manufacturing process. Yield of test structures on a testline is often used to predict the yield of functional integrated circuitries in the die area.
Shown in FIG. 1A is a plan view of a portion of a semiconductor wafer substrate layer 5 on which conventional parametric testlines are formed. A parametric testline 20 is formed in a scribe line area 10 between adjacent wafer dies 15. Each testline is made up by a serial number of aligned probe pads. Each probe pad 25 has a square shape and may be made from metal or other electrically conductive materials. Probe pads on a testline are electrically connected to a plurality of DUTs 30 formed between adjacent probe pads beneath the probe pad layer. Pluralities of test lines with different DUTs are formed in scribe line areas across the substrate. The DUTs 30 are test structures in the form of resistors, capacitors, inductors, diodes, transistors, or the like, designed to measure device parameters, such as MOSFET Vt, contact/via chain resistance, sheet capacitance, gate oxide breakdown voltage, and the like. By studying these parameters, it is possible to monitor, improve and refine a semiconductor production process.
FIG. 1B is a schematic cross-section view of a portion of an exemplary parametric testline 20 along the longitudinal direction AA′ as shown in FIG. 1A. To avoid repetition, like numerals and letters used in FIG. 1A will be used for the various elements in the coming figures. Also, reference numbers described in FIG. 1A may not be described again in detail herein. As illustrated in FIG. 1B, a conventional parametric testline 20 is generally composed of two major parts. The first part is a generic framework testline structure, as shown in a cross-section view, in correspondence with a certain technology generation. This part of the testline structure comprises a substrate layer 5, an insulating layer 8 formed atop the substrate layer 5 and a plurality of probe pads 25 of identical shape formed with the same pad pitch on the top surface of insulating layer 8. Each probe pad 25 is electrically connected to an underlying stacking via structure, which comprises a square shaped metal piece on each metal layer coupled to each other through one or more vias. A probe pad structure (a probe pad 25 and the stacking via structure formed thereunder) is separated from an adjacent probe pad structure by insulating material 8. This part of the testline structure defines testline parameters such as line length, line width, probe pad size, probe pad pitch, test pattern size, and so on. The second part of a testline structure consists of a plurality of DUTs 30, for example the R (resistance) and C (capacitance) shown in the schematic view in FIG. 1B, which are formed in the test pattern areas between adjacent probe pads 25 on a testline 20. This part of the testline structure differentiates one testline from another through DUTs 30 designed to monitor different process parameters or to evaluate different device structures and circuit products. In practice, a layout of a generic framework testline structure is first provided to a testline designer. The testline designer will then “customize” the generic framework structure by “plugging” customized DUTs into the predefined framework, using the predetermined size of a test pattern area as a physical constraint. In FIG. 1B, a DUT 30 in the form of a doped silicon substrate sheet resistor R is “plugged” into the test pattern area between pad 1 and pad 2 and is electrically connected to the M1 (first metal layer) piece of pad 1 and the M1 piece of Pad 2. As another example, a DUT 30 in the form of a capacitor C, which is designed to measure the M3 to M2 dielectric leakage current, is “plugged” into the test pattern area between pad 2 and pad 3 and is electrically connected to the M2 piece of pad 2 and the M3 piece of pad 3.
Following the continuous scale down in device feature sizes in an integrated circuit in order to meet the increasing demand of integrating more complex circuit functions on a single chip, a similar trend had been urged upon the size and structure of a parametric testline. That is the area of a testline line must shrink with each technology generation to facilitate more wafer areas for functional integrated circuitries. As an example, when semiconductor processing technology upgrades from 130 nm technology node to 90 nm technology node, a typical test pattern area on a prior art parametric test line has decreased from about 8000 μm2 to about 3500 μm2, a reduction of more than 50%. This trend will continue with greater magnitude while technology updating continues. As a result, at a certain point, the size of a test pattern area on a prior art parametric testline will become too small to accommodate certain types of DUTs.
On the other hand, the continuing scale-down of device feature sizes and increased circuit complexity in an integrated circuit has imposed new demands on the existing parametric testline structure. One of these demands is that testlines corresponding to advanced processing technology must include a large amount of test structures of different types and dimensions to meet the test needs for advanced semiconductor devices and complex integrated circuits. Another demand comes from the need of design-for-manufacturability (DFM) in advanced technology, where much more testing resources are needed on a testline in order to analyze the correlation of a specific layout style to a process yield and obtain a preferred set of layout style leading to a predictable manufacturing yield. A further demand on a parametric testline comes from the semiconductor process R&D field, where a large number of test resources are required to conduct extensive design-on-experiment (DOE) and statistical split activities critical in reaching a process flow of high manufacturing yield in advanced technology. The demands mentioned above are all calling for testlines capable of offering more test pattern areas and to accommodate more DUTs of various types and dimensions.
In view of the trends described above and other issues facing a conventional parametric testline and the ever increasing testing tasks demanded by advanced technologies, there is a need for improved testline structures capable of housing more DUTs and DUTs of various dimensions on a shrunk testline area.